1. Field of the Invention
The invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.
2. Background Art
High integration of devices by downscaling on two dimensional silicon substrate surfaces is reaching limitations. A major purpose of the high integration of semiconductor memory is to achieve large capacity by reducing the bit cost. Strategies include stacking transistors three dimensionally.
However, methods that simply pattern and stack one layer at a time lead to higher costs due to the increase in the number of processes necessary for the stacking. In particular, increasing the number of lithography processes for patterning the transistor structure is a main cause of higher costs, and the trend of higher costs is significant when increasing the number of layers. Therefore, reducing the silicon surface area per bit by stacking does not reduce the bit cost as much as downscaling on the silicon surface; and as a method to increase capacity, problems remain.
To solve such problems, the inventors have invented a nonvolatile semiconductor memory device having a collectively patterned stacked structure (for example, refer to JP-A 2007-266143 (Kokai)). One feature of the collectively patterned stacked structure is that the number of lithography processes necessary for patterning does not depend on the number of stacks. Therefore, in the case where the number of stacks of the collectively patterned stacked structure increases, the silicon surface area per bit is reduced, and it is possible to reduce the bit cost.
On the other hand, a one-time programmable memory (OTP memory) cannot perform the erasing of data or the rewriting of data and only reading is possible after once writing the data.
The collectively patterned stacked structure may be applied also to OTP memory. For example, the OTP memory may be formed by forming silicon pillars having circular columnar configurations to pierce multiply stacked electrode films and forming silicon oxide films at the intersection points between the multiple layers of electrode films and the silicon pillars.
In other words, for example, the silicon pillars may be an n-type semiconductor, the stacked electrode films may be a p-type semiconductor; and after destructing a silicon oxide film, PN junction diodes can be formed at the intersections between the silicon pillars and the electrode films.
In such a case, it is necessary to suppress the voltage drop of the silicon pillar forming the current path to each of the diodes. Conversely, in the case where high concentration doping of the silicon pillar is performed to reduce the resistance of the silicon pillar and high concentration doping of the electrode film is performed accordingly, the n-type and p-type semiconductors doped with high concentrations contact each other after the destruction of the silicon insulating film; a larger leak current occurs in the reverse direction; and signal detection is difficult. Conversely, in the case where the doping concentration of the silicon pillar is reduced, the region of the depletion layer occurring from the n-type semiconductor forming the electrode film enlarges; the leak current between the electrode films above and below increases; and as expected, the signal detection is difficult. Also, reducing the doping concentration of the silicon pillar undesirably causes the resistance of the silicon pillar to increase. Thus, in conventional PN diode structures, the voltage drop of the silicon pillar, the increase of the leak current in the reverse direction, the increase of the leak current between the electrode films above and below, or the increase of the resistance of the silicon pillar may occur; and there is room for improvement to obtain more stable operations.